As the storage capacity of integrated circuit memories continues to increase through higher integration, associated memory cell defects rise accordingly, due to increased complexity in manufacturing processes, leading to degradation of production yield. In general, it is difficult to render a memory device having no defective cells. Therefore, various attempts have been made to improve the production yields of the highly integrated memory devices.
It is preferable to improve the manufacturing process to suppress the generation of the defective cells; but there are limitations. Thus, other ways for improving production yields in large integrated circuit memories have been proposed. One of the ways for enhancing production yield is a redundancy technique for which a constitution of the memory device is designed to repair defective regions born therein during the manufacturing process. According to the redundancy technique, a main memory cell array for storing binary data is arranged together with an array formed of redundant memory cells to implement the defective cells in rows and columns.
In general, a redundant cell array can be classified as a row redundant array for substituting defective cells in rows, or as a column redundant array for substituting defective cells in columns. Substituting the defective cells with redundant cells is accomplished by storing defective addresses, i.e. information on positions of the defective cells, and by determining whether or not the defective addresses are identical with external addresses. Such circuits, along with the redundant cell array, compose a redundancy circuit, providing a memory device capable of operating normally, free from invalid operations due to the defective cells.
In a memory device having the redundancy circuit, evaluation of production yield requires detection of detect whether a redundant array is utilized. A technique for storing the repair information is disclosed in U.S. Pat. No. 5,677,917 entitled “Integrated Circuit Memory Using Fusible Links In A Scan Chain” by Wheelus et. Al. on Oct. 14, 1997.
FIG. 1 is a schematic diagram of a fuse circuit disclosed in Wheelus. Referring to FIG. 1, the fuse circuit is formed of a fuse 10, N-channel metal-oxide semiconductor (NMOS) transistors 12 and 14, and inverters 16 and 18. The fuse 10 is made of polysilicon that is able to be cut out, or otherwise opened, by a laser, and connected between power supply voltage VDD and sensing node 15. The NMOS transistor 12 has a gate coupled to the power supply voltage VDD, and connects the sensing node 15 to ground voltage VSS. The NMOS transistor 14 is connected between the sensing node 15 and the ground voltage VSS. The sensing node 15 is connected to the output terminal of the fuse circuit through inverters 16 and 18. The gate of the NMOS transistor 14 is coupled to output of inverter 16 (and input of the inverter 18). Inverter 16 is connected to drain of NMOS transistors 12 and 14, and to the gate of NMOS transistor 14. Inverter 18 is connected to the output terminal of inverter 16, and provides output signal D.
Operation of the fuse circuit shown in FIG. 1 is described as follows. When the fuse 10 connects the power supply voltage VDD to the sensing node 15 so as to set the output signal D into a high level (i.e., the fuse 10 is not cut out), the power supply voltage VDD is applied to the input terminal of the inverter 16, and then the inverter 16 provides low level. Thus, the NMOS transistor 14 maintains a non-conductive state, and the inverter 18 provides the signal D at a high level. Meanwhile, if the fuse 10 does not connect the power supply voltage VDD to the sensing node 15, so as to set the output signal D into low level (i.e., the fuse 10 is cut out), NMOS transistor 12 pulls an output voltage of the inverter 16 down to low level. That is, the NMOS transistor 12 operates as a pull-down transistor. The inverter 16 applies a signal of high level to the gate of NMOS transistor 14 and the input terminal of the inverter 18. Thus, NMOS transistor 14 becomes conductive to lower the input terminal of the inverter 16 down to low level, and thereby the inverter 18 generates the output signal D at a low level.
As described above, a voltage level of the output signal D generated from the conventional fuse circuit is dependent upon a programmed state on the fuse 10, i.e. whether or not the fuse 10 is cut out. As semiconductor memory device density is increased to scale down topological size of circuit elements including the fuses, the cut out technique for the fuses becomes more and more of a challenge. An incorrect (or failed) cut out of the fuses results in an invalid programming in the fuse circuit, causing degradation of the production yield.